[PicForth] isr weirdness+workaround - stray data mem writes

[David McNab]

Hi,

I've been tracking an annoying intermittent problem with ISR side-effects.

The symptom is that stray writes are occurring to weird locations.

I've isolated it to an area of the ISR which, when a Timer1 interrupt 
happens, executes nested if/else/then statements, which manipulate 
program variables. When I disable this code, no stray writes occur. But 
when I enable it, I see these stray writes.

It would be a mammoth task to reproduce a simple minimal example which 
reproduces this behaviour, especially since the stray writes can occur 
as frequently as 8 seconds, or as rarely as every 20 minutes or so.

I've seen some weirdness before with PCLATH bits not being correctly set 
within control structure blocks such as 'if' and 'while'. As mentioned 
in earlier messages, I've worked around this by putting 'forth> 
no-cbank' statements inside the control statements.

So for this case, as an experiment, I tried putting a 'restore-bank' 
inside the 'if' part of the code. So far, I haven't seen any stray writes.

Sorry if this account is a bit vague. But it's the best I can do at the 
moment.

-- 
Cheers
David